(1) Field of the Invention
The present invention relates to methods of fabricating shallow trench isolation and, more particularly, to methods of fabricating shallow trench isolation filled with two or more dielectrics for isolation, coupling, or stress relief in the fabrication of integrated circuits.
(2) Description of the Prior Art
Shallow-trench isolation (STI) is the most popular isolation scheme for advanced CMOS (e.g. 0.25 um and beyond). However, as the spacing of STI is continuously scaled down to  less than 0.15 um, there is significant field penetration into the channel (or body) area from the bias of adjacent source/drain junctions. This is discussed in xe2x80x9cCharacteristics of CMOS device isolation for the ULSI agexe2x80x9d, A. Bryant, W. Hansch, and T. Mii, International Electron Device Meetings, p.671, 1994, xe2x80x9cThree-dimensional DIBL for shallow-trench isolation MOSFET""sxe2x80x9d, C. Wang, P. Zhang, IEEE Trans. on Electron Device, V.46, No. 1, p.139, 1999, and xe2x80x9cThe impact of isolation pitch scaling on Vth fluctuation in DRAM cell transistors due to neighboring drain/source electric field penetrationxe2x80x9d, J. H. Sim, J. K. Lee, and K. Kim, Symposium of VLSI technology, p.32-33, 1998. Therefore, such xe2x80x9cnon-perfectxe2x80x9d isolation from STI can result in undesirable effects, such as threshold voltage (Vt) fluctuations, with increasing impact in future technology with smaller STI spacing.
One way to eliminate such field penetration effect, a metallic-shielded STI, was proposed in xe2x80x9cHigh-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM""sxe2x80x9d, J. H. Sim, J. K. Lee, and K. Kim, IEEE Transaction on Electron Devices, Vol. 46, No. 6, p.1212-1217, 1999. In this proposal, a layer of conducting material (e.g. doped poly) fills the isolation trench after liner oxidation. The grounded conducting material in the trench can provide good shielding and therefore can eliminate transistor""s narrow-width effect and Vt fluctuations. There is certainly continuous need for better isolation structure and process.
Interestingly, such field penetration effect due to xe2x80x9cnon-perfectxe2x80x9d STI may also be utilized for forming vertical resistors, FETs, and circuits as disclosed in co-pending U.S. patent applications Ser. No. 10/268,465 filed Oct. 10, 2002 to the same inventor. Thus, the coupling effect through STI may also be useful if the coupling through STI is enhanced.
Furthermore, the effect of stress in the active area is discussed in xe2x80x9cNew mechanical reliability issues for deep-submicron devicesxe2x80x9d, H. Miura and S. Ikeda, Symposium of manufacturing technology workshop, Taiwan, p.140-147, 1998. It is desired to control this stress, especially as it relates to isolation formation. Other related literature includes co-pending U.S. patent application Ser. No. 10/444,874 (TSMC-02-161), xe2x80x9cCarrier mobility enhancement in strained Si-on-insulator fabricated by wafer bondingxe2x80x9d by L. J. Huang et al, Symposium VLSI Tech., Dig. Tech. Papers, Kyoto, Japan, p. 57-58, 2001; xe2x80x9cFabrication and analysis of deep sub-micron strained-Si n-MOSFETsxe2x80x9d, by K. Rim et al, IEEE Trans. Electron Dev., vol. 47, no. 7, p. 1406-1415, July 2000; xe2x80x9cStrained Si surface channel MOSFETs for high performance CMOS technologyxe2x80x9d, by K. Rim, ISSCC, paper #7.3, p. 116-117, 2001; xe2x80x9cCarrier mobility and process stability of strained Si n- and p-MOSFETs on SiGe virtual substratesxe2x80x9d, by M. T. Currie et al, J. Vacuum Science Technology B, vol. 19, no. 6, p.2268, November/December 2001; xe2x80x9cEnhanced performance in sub-100 nm CMOSFETs using strained epitaxial Silicon-Germaniumxe2x80x9d, by Y. C. Yeo et al, IEDM, p. 753, 2000; xe2x80x9cSiGe HBT technology: a new contender for Si-based RF and microwave circuit applicationsxe2x80x9d, by J. D. Cressler, IEEE Trans. Microwave and Techniques, V. 46, No. 5, p.572-589. Related patents include U.S. Pat. No. 6,297,128 to H. S. Kim et al and U.S. Pat. No. 6,037,237 to M. H. Park et al.
U.S. Pat. No. 6,074,909 to Gruening shows a STI and a vertical transistor process. U.S. Pat. No. 6,255,176B1 to Kim et al shows a STI with a high dielectric constant material. U.S. Pat. No. 6,194,283B1 to Gardner et al discloses a low dielectric constant spacer layer in a STI process. U.S. Pat. No. 5,742,091 to Hebert shows a low dielectric constant material as a liner or as a fill layer in a STI process.
According, it is an object of the invention that shallow trench isolation regions on the same chip are filled with two or more different dielectric materials.
It is another object of the invention that one shallow trench is filled with a low dielectric constant (k) material for isolation and another shallow trench be filled with a high k material for coupling on the same chip.
Another object of the invention is to provide a method for fabricating shallow trenches filled with two or more different dielectric materials.
Yet another object is to provide a method for fabricating shallow trenches filled with two or more different materials.
A further object of the invention is to provide a method of fabricating a capacitor structure formed by a shallow trench filled with a high k material.
A still further object is to provide a method of fabricating a vertical transistor formed by a shallow trench filled with a high k material.
Yet another object is to provide a method for controlling stress in the silicon active area of an integrated circuit by filling shallow trenches with dielectrics having different thermal expansion coefficients.
In accordance with the objects of this invention, a method for forming shallow trenches having different trench fill materials is achieved. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling said trenches. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches and planarized to the stop layer leaving the second layer within the subset of trenches to complete fabrication of shallow trenches having different trench fill materials. The trench fill materials may be dielectric layers having different dielectric constants or they may be a dielectric layer and a conducting layer. The method can be extended to provide three or more different trench fill materials.
Also in accordance with the objects of the invention, a method for fabricating a n+ to n+ capacitor is achieved. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling the trenches wherein the first layer comprises a dielectric material having a first dielectric constant. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches wherein the second layer comprises a dielectric material having a second dielectric constant higher than the first dielectric constant. The second layer is planarized to the stop layer leaving the second layer within the subset of trenches. N+ junctions are formed on either side of one of the subset of trenches wherein the trench forms a capacitor dielectric of the n+ to n+ capacitor. A p+ to p+ capacitor can be formed in a similar way within an n-well.
Also in accordance with the objects of the invention, a method for fabricating a vertical MOSFET is provided. A deep n-well is formed within a substrate. A stop layer is provided on the substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling the trenches wherein the first layer comprises a dielectric material having a first dielectric constant. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches wherein the second layer comprises a dielectric material having a second dielectric constant higher than the first dielectric constant. The second layer is planarized to the stop layer leaving the second layer within the subset of trenches. Within the deep n-well, a first n+ junction is formed on one side of one of the subset of trenches, called a high-k trench, and a p-well is formed underlying the first n+ junction wherein the p-well forms the body of a vertical MOSFET device. A second gate n+ junction is formed on another side of the high-k trench wherein the second n+ junction is formed deeper than the first n+ junction and wherein a p-base is formed underlying the second n+ junction wherein the vertical MOSFET device is turned on by forming an inversion layer at a sidewall of the body adjacent to the high-k trench. A vertical PMOSFET can be fabricated in a similar way using a deep p-junction as the gate in a p-substrate with an n-base implant.
Also in accordance with the objects of the invention, a method for controlling stress in silicon active areas is provided. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling the trenches wherein the first layer comprises a dielectric material having a thermal coefficient higher than that of silicon. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches wherein the subset of the trenches surrounds second silicon active areas and wherein the remaining trenches surround first silicon active areas. A second layer is deposited over the stop layer and within the subset of trenches wherein the second layer comprises a dielectric material having a thermal coefficient lower than that of silicon. The second layer is planarized to the stop layer leaving the second layer within the subset of trenches wherein controlled tensile stress is applied to the first silicon active areas and wherein controlled compressive stress is applied to the second silicon active areas.
Also in accordance with the objects of the invention, a method for controlling stress in a silicon active area is achieved. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate wherein the trenches surround a silicon active area. A first layer is deposited over the stop layer and filling the trenches wherein the first layer comprises a dielectric material having a thermal coefficient higher than that of silicon. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches wherein the subset of trenches surround the silicon active area in a first direction and wherein the remaining trenches surround the silicon active area in a second direction perpendicular to the first direction. A second layer is deposited over the stop layer and within the subset of trenches wherein the second layer comprises a dielectric material having a thermal coefficient lower than that of silicon. The second layer is planarized to the stop layer leaving the second layer within the subset of trenches wherein compressive stress is applied to the silicon active area in the first direction and tensile stress is applied to the silicon active area in the second direction.